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RLP1N08LE
Data Sheet April 1999 File Number
2252.3
1A, 80V, 0.750 Ohm, Current Limited, N-Channel Power MOSFET
The RLP1N08LE is a semi-smart monolithic power circuit which incorporates a lateral bipolar transistor, two resistors, a zener diode, and a PowerMOS transistor. Good control of the current limiting levels allows use of these devices where a shorted load condition may be encountered. "Logic level" gates allow this device to be fully biased on with only 5V from gate to source. The zener diode provides ESD protection up to 2kV. These devices can be produced on the standard PowerMOS production line. Formerly developmental type TA09842.
Features
* 1A, 80V * rDS(ON) = 0.750 * ILIMIT at 150oC = 1.5A Maximum * Built-in Current Limiting * ESD Protected * Controlled Switching Limits EMI and RFI * Specified for 150oC Operation * Temperature Compensated Spice Model Provided * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RLP1N08LE PACKAGE TO-220AB BRAND L1N08LE
Symbol
D
NOTE: When ordering, use the entire part number.
G
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
6-435
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RLP1N08LE
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RLP1N08LE Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Electrostatic Voltage at 100pF, 1500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ESD Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Power Dissipation Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 80 80 2 Self Limited 5.5 30 0.24 -55 to 150 300 260 V W W/oC
oC oC oC
UNITS V V kV
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, Figure 7 VGS = VDS, ID = 250A, Figure 8 VDS = 65V, VGS = 0V TC = 25oC TC = 150oC MIN 80 1 TC = 25oC TC = 150oC TC = 25oC TC = 150oC 1.8 1.1 1 1 TO-220AB Human Model (100pF, 1.5k) 2000 TYP MAX 2 1 50 50 0.750 1.5 3 1.5 6.5 1.5 5 7.5 5 12.5 4.17 62 UNITS V V A A A A A s s s s s s
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2)
IGSS rDS(ON)
VGS = 5V, TC = 150oC ID = 1A, VGS = 5V Figure 6 VDS = 15V, VGS = 5V Figure 3
Limiting Current
IDS(Lim)
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Electrostatic Voltage
t(ON) td(ON) tr td(OFF) tf t(OFF) RJC RJA ESD
VDD = 30V, ID = 1A, VGS = 5V, RGS = 25 RL = 30
V
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time NOTES: 2. Pulsed: pulse duration = 300s maximum, duty cycle = 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr ISD = 1A ISD = 1A TEST CONDITIONS MIN TYP MAX 1.5 1 UNITS V ms
6-436
RLP1N08LE Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A)
Unless Otherwise Specified
10 TJ = MAX RATED ID MAX AT 25oC 100s 1ms 10ms DC
ID MIN AT 150oC 1.0 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
0.6 0.4
0.2 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 VDSS MAX = 80V 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
NORMALIZED DRAIN TO SOURCE CURRENT 2.0 IDS, DRAIN TO SOURCE CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. VDS = 10V, VGS = 5V 1.5
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
3.0 TC = 25oC 2.5 2.0 1.5 3V 1.0 0.5 0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 2V 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 8V 6V 5V 4V VGS = 10V
1.0
0.5
0 -50
0 50 100 TC, CASE TEMPERATURE (oC)
150
FIGURE 3. NORMALIZED CURRENT LIMIT vs CASE TEMPERATURE
4.2 PULSE TEST PULSE DURATION = 80s 3.5 DUTY CYCLE = 0.5% MAX VDS = 15V 2.8 2.1 1.4 0.7 0 150oC 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
FIGURE 4. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
-55oC
2.0
VGS = 5V, ID = 1A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX.
25oC
1.5
1.0
0.5
0
2.5 5.0 VGS, GATE TO SOURCE VOLTAGE (V)
7.5
0 -50
0
50
100
150
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 5. TRANSFER CHARACTERISTICS
FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
6-437
RLP1N08LE Typical Performance Curves
1.4 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A
Unless Otherwise Specified (Continued)
1.2 1.1 NORMALIZED GATE THRESHOLD VOLTAGE 1.0
VGS = VDS ID = 250A
1.2
1.0
0.9
0.8
0.8 0.7 0.6 -50
0.6
0.4 -50
0
50
100
150
0
50
100
150
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
VDD
500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD + 200 CRSS 100 CISS RGS COSS 0
RL VDS VGS G D
400 C, CAPACITANCE (pF)
300
0
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
25
S
FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 10. SWITCHING TEST CIRCUIT
20 VDS, DRAIN TO SOURCE VOLTAGE (V)
15
1oC/W 2oC/W
VDS, DRAIN TO SOURCE VOLTAGE (V)
HSTR = 0oC/W
TJ = 150oC ILIM = 1.5A RJC = 4.17oC/W
80
60 DUTY CYCLE = 20% 10% 5% 2% 1%
FREE AIR RJC = 80oC/W
10 5oC/W 10oC/W 25oC/W 0 25
40
5
20
50% MAX PULSE WIDTH = 100ms TJ = 150oC, ILIM = 1.5A, RJC = 4.17oC/W 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC)
50
75
100
125
150
0 25
TA, AMBIENT TEMPERATURE (oC)
NOTE: Heatsink thermal resistance = 2oC/W FIGURE 11. DC OPERATION IN CURRENT LIMITING FIGURE 12. MAXIMUM VDS vs TA IN CURRENT LIMITING
6-438
RLP1N08LE Typical Performance Curves
80 VDS, DRAIN TO SOURCE VOLTAGE (V) MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RJC = 4.17oC/W 5%
Unless Otherwise Specified (Continued)
80 2% 1% VDS, DRAIN TO SOURCE VOLTAGE (V) MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RJC = 4.17oC/W 5% 10% 40 2% 1%
60
60
10% 40 DUTY CYCLE = 20%
DUTY CYCLE = 20% 20 50% 0 25 50 75 100 125 150
20 50%
0 25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
TA, AMBIENT TEMPERATURE (oC)
NOTE: Heatsink thermal resistance = 5oC/W FIGURE 13. MAXIMUM VDS vs TA IN CURRENT LIMITING
80 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Heatsink thermal resistance = 10oC/W FIGURE 14. MAXIMUM VDS vs TA IN CURRENT LIMITING
80 VDS, DRAIN TO SOURCE VOLTAGE (V)
60
MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RJC = 4.17oC/W
1%
DUTY CYCLE = 1%
60
MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RJC = 4.17oC/W
DUTY CYCLE = 2% 40 5%
40
20
10% 20% 50%
20
2% 10% 20% 50% 5%
0 25
50
75
100
125
150
0 25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
TA, AMBIENT TEMPERATURE (oC)
NOTE: Heatsink thermal resistance = 25oC/W FIGURE 15. MAXIMUM VDS vs TA IN CURRENT LIMITING
10 RJC =
NOTE: No external heatsink. FIGURE 16. MAXIMUM VDS vs TA IN CURRENT LIMITING
10 RJC = 4.17oC/W
4.17oC/W 8
8 TIME TO 150oC (s) 125oC 6 100oC 75oC 50oC TIME TO 150oC (s) STARTING TEMP = 25oC
STARTING TEMP = 25oC 6 125oC 4 100oC 75oC 50oC
4
2
2
0
0
5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V)
20
0
0
5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V)
20
NOTE: Heatsink thermal resistance = 2oC/W Heatsink thermal capacitance = 4j/oC FIGURE 17. TIME TO 150oC IN CURRENT LIMITING
NOTE: Heatsink thermal resistance = 5oC/W Heatsink thermal capacitance = 2j/oC FIGURE 18. TIME TO 150oC IN CURRENT LIMITING
6-439
RLP1N08LE Typical Performance Curves
10
Unless Otherwise Specified (Continued)
RJC = 4.17oC/W
10
RJC = 4.17oC/W
8 TIME TO 150oC (s) TIME TO 150oC (s) STARTING TEMP = 25oC 6 125oC 100oC 75oC 50oC 4
8 STARTING TEMP = 25oC 6 125oC 4 100oC 75oC 50oC
2
2
0
0
5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V)
20
0
0
5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V)
20
NOTE: Heatsink thermal resistance = 10oC/W Heatsink thermal capacitance = 1j/oC FIGURE 19. TIME TO 150oC IN CURRENT LIMITING
10
NOTE: Heatsink thermal resistance = 25oC/W Heatsink thermal capacitance = 0.5j/oC FIGURE 20. TIME TO 150oC IN CURRENT LIMITING
8 TIME TO 150oC (s)
6 STARTING TEMP = 25oC 4 125oC 2 100oC 75oC 50oC 20
0
0
5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: No external heatsink. FIGURE 21. TIME TO 150oC IN CURRENT LIMITING
6-440
RLP1N08LE
Temperature Dependence of Current Limiting and Switching Speed
The RLP1N08LE is a monolithic power device which incorporates a logic level PowerMOS transistor with a resistor in series with the source. The base and emitter of a lateral bipolar transistor is connected across this resistor, and the collector of the bipolar transistor is connected to the gate of the PowerMOS transistor. When the voltage across the resistor reaches the value required to forward bias the emitter base junction of the bipolar transistor, the bipolar transistor "turns on". A series resistor is incorporated in series with the gate of the PowerMOS transistor allowing the bipolar transistor to drive the gate of the PowerMOS transistors to a voltage which just maintains a constant current in the PowerMOS transistor. Since both the resistance of the resistor in series with the PowerMOS transistor source and voltage required to forward bias the base emitter junction of the bipolar transistor vary with the temperature, the current at which the device limits is a function of temperature. This dependence is shown in figure 3. The resistor in series with the gate of the PowerMOS transistor results in much slower switching than in most PowerMOS transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable, and a minimum as well as maximum fall time is given in the device characteristics for this type.
Duty Cycle Operation of the RLP1N08LE
In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLP1N08LE is mounted has a very large thermal storage capability, so for pulse widths of less than 100 milliseconds, the temperature of the header can be considered a constant case temperature calculated simply as:
T C = ( V DS x I D x D x R CA ) + T AMBIENT (EQ. 2)
Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 150oC and using the TC calculated above, the expression for maximum VDS under duty cycle operation is:
150 - T C V DS = -----------------------------------------I LIM x D x R JC (EQ. 3)
These values are plotted as Figures 12 thru 16 for various heat sink thermal resistances.
Limited Time Operations of the RLP1N08LE
Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 milliseconds and the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as figures 17 thru 21 give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 150oC junction termperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur.
DC Operation of the RLP1N08LE
The limit of the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown as Figure 11. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This device, like most Power MOSFET devices today, is limited to 150oC. The maximum voltage allowable can, therefore be expressed as:
( 150 C - T AMBIENT ) V DS = ---------------------------------------------------------I LIM x ( R JC + R CA )
o
(EQ. 1)
6-441
RLP1N08LE Spice Model
(RLP1N08LE)
.SUBCKT RLP1N08LE 2 1 3; rev 09/16/91 *Nominal Temperature = 25oC .MODEL MOSMOD NMOS (VTO=1.7 KP=2.1 IS=1e-30 N=10 TOS=1 L=1u W=1u) Vto 21 6 0.33 Rsource 8 7 RDSMOD 0.28 Rdrain 5 16 RDSMOD 0.2 .MODEL RDSMOD RES (TC1=7.54E-3 TC2=2.23E-5) .MODEL RVTOMOD RES (TC1=-2.23E3 TC2=-5.29E-7) .MODEL RVTOMOD2 RES (TC1=0 TC2=0) Ebreak 11 7 17 18 107.3 .MODEL RBKMOD RES (TC1=1.11E-3 TC2=-6.83E-7) .MODEL DBKMOD D (RS=2.78 TRS1=-8.88E-3 TRS2=2.55E-5) .MODEL DBDMOD D (IS=9.91E-15 RS=3.01E-1 TRS1=3.79E-3 TRS2=1.11E-6 +CJO=4.32E-10 Cin 6 8 3.75E-10 Ca 12 8 6.5E-10 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-1) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=-3) .MODEL DPLCAPMOD D (CJO=2E-10 IS=1e-30 N=10) Cb 12 14 6.5E-10 .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.65 VOFF=3.35) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.35 VOFF=-1.65) Rgate 9 20 4.48E3 Lgate 1 9 9.5E-10 Ldrain 2 5 2.5E-9 Lsource 3 7 2.5E-9 Dbody 7 5 DBDMOD Dbreak 5 11 DBKMOD Dplcap 10 5 DPLCAPMOD Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evto 20 6 18 8 1 It 8 17 1 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 Rbreak 17 18 RBKMOD 1 Rin 6 8 1e9 Rvto 18 19 RVTOMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 8 19 DC 1 *Current Limiting Control Section .MODEL RSMOD RES (TC1=3.2E-3) Q Control 20 8 7 QMOD 10 .MODEL QMOD NPN (BF=5 VJE=0.5) *ESD Protection DESD 7 9 DESMOD .MODEL DESMOD D(BV=7.185 TBV1=3.5E-4 TBV2=2.2E-6) .ENDS
TT=2E-7
6-442
RLP1N08LE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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